Semiconductors are used in integrated circuits for electronic applications, including radios, televisions, cell phones, and personal computing devices, as examples. One type of semiconductor device is a semiconductor storage device, such as a dynamic random access memory (DRAM) and flash memory, which uses a charge to store information.
Various memory types are in common use to digitally store a substantial amount of data. DRAMs have moderate cost, are very fast and can have access times on the order of a few nanoseconds, but lose the stored data upon loss of electrical power, i.e., they are “volatile.” Present “flash” memories are non-volatile, are more expensive perhaps by a factor of ten, and have access times near a microsecond. Hard-disk drives are substantially lower in cost than DRAMs, are non-volatile, but have access times generally greater than a millisecond. Further application considerations for each technology include limitations on the number of times a memory cell can be written or read before it deteriorates, how long it reliably retains data, its data storage density, how much energy it consumes, the need for integral mechanical devices such as for disk drives and tapes, and the complexity and expense of associated circuitry. In addition, memory devices based on charge storage generally need to be rewritten each time they are read, adding to their complexity and cost. Considering these limitations, there is now no ideal technology for general applications. Magnetic random access memory (MRAM) as described below appears to have properties that position it well for widely accepted digital memory applications, overcoming many of these limitations.
Spin electronics, which combines semiconductor technology and magnetics, i.e., which utilizes both the discrete electron charge and magnetic moment of electrons, is a relatively recent development in semiconductor memory devices. The spin of an electron, rather than the charge, is used to indicate the presence of a logic “1” or “0”. One such spin electronic device is a resistive memory device referred to as a magnetic random access memory, which includes conductive lines usually positioned perpendicular to one another in different metal layers, the conductive lines sandwiching a magnetic stack which functions as a memory cell. The place where the conductive lines intersect is called a cross-point. A current flowing through one of the conductive lines generates a magnetic field around the conductive line and orients the magnetic polarity of one layer of the magnetic stack. A current flowing through the other conductive line induces a superimposed magnetic field and can partially turn the magnetic polarity, also. Digital information, represented as a “0” or “1”, is storable in the alignment of magnetic moments in the magnetic stack. The resistance of the magnetic stack depends on the moment's alignment. The stored state is read from the magnetic stack by detecting the component's resistive state. An array of memory cells may be constructed by placing the conductive lines in a matrix structure having rows and columns, with the magnetic stack being placed at the intersection of the conductive lines.
A key advantage of MRAMs compared to traditional semiconductor memory devices, such as DRAMs, is that MRAMs are non-volatile upon removal of electrical power. This is advantageous because a personal computer (PC) utilizing MRAMs could be designed without a long “boot-up” time as with conventional PCs that utilize DRAMs, as an example. Moreover, MRAMs do not need to be rewritten when they are read. In addition, MRAMs have the potential for read/write speeds in the range of a few nanoseconds, which compares favorably with fast memory technologies now available.
FIG. 1 illustrates a magnetic tunnel junction (MTJ) stack capable of storing one bit that comprises a resistive or magnetic memory cell. The terms “memory cell,” “MTJ,” “MTJ cell,” and “MTJ stack” are used interchangeably herein and refer to the MTJ shown in FIG. 1. The MTJ comprises at least two ferromagnetic layers M1 and M2 that are separated by a tunnel layer TL. The MTJ stack is positioned at the cross-point of two conductors referred to as a wordline WL and a bitline BL. One magnetic layer M1 is referred to as a free layer or a storage layer, and the other magnetic layer M2 is referred to as a fixed layer or a reference layer. Two publications describing the art of MRAMs are S. Tehrani, et al., “Recent Developments in Magnetic Tunnel Junction MRAM,” IEEE Trans. on Magnetics. Vol. 36, Issue 5, September 2000, pp. 2752–2757, and J. DeBrosse, A. Bette et al., “A High Speed 128-kb MRAM Core for Future Universal Memory Applications,” IEEE Journal of Solid State Circuits, Vol. 39, Issue 4, April 2004, pp. 678–683, which are both hereby referenced and included herein. The magnetic orientation of the free layer M1 can be changed by the superposition of the magnetic fields caused by a programming current IBL that is run through the bitline BL and a programming current IWL that is run through the wordline WL. A bit, e.g., a “0” or “1”, may be stored in the MTJ stack by changing the orientation of the field of the free magnetic layer relative to that of the fixed magnetic layer. If both magnetic layers M1 and M2 have the same orientation, the MTJ stack has a lower resistance RC. The resistance RC is higher if the magnetic layers have opposite magnetic orientations.
FIG. 2 illustrates a memory cell of an MRAM device 10 from an array of MRAM device having a select transistor X1. In some MRAM array designs, the MTJ stack is combined with a select transistor X1, as shown in FIG. 2, which is a cross-sectional view of a 1T1MTJ design (one transistor and one MTJ stack). The 1T1MTJ design uses the select transistor X1 for fast access of the MTJ during a read operation. A schematic diagram of the MTJ stack and select transistor X1 is shown in FIG. 3. A bitline BL is coupled to one side of the MTJ stack, and the other side of the MTJ stack is coupled to the drain D of the select transistor X1 by metal layer MX, via VX, and a plurality of other metal and via layers, as shown. The source S of the transistor X1 is coupled to ground (GND). X1 may comprise two parallel transistors that function as one transistor, as shown in FIG. 2. Alternatively, X1 may comprise a single transistor, for example. The gate G of the transistor X1 is coupled to a read wordline (RWL), shown in phantom, that is preferably positioned in a different direction than, e.g., perpendicular to the bitline BL direction.
The select transistor X1 is used to access the memory cell's MTJ. In a read (RD) operation during current sensing, a constant voltage is applied at the bitline BL. The select transistor X1 is switched on, e.g., by applying a voltage to the gate G by the read wordline RWL, and current then flows through the bitline BL, the magnetic tunnel junction MTJ, over the MX layer, down the metal and via stack, through the transistor drain D, and through the transistor X1 to ground GND. This current is then measured and is used to determine the resistance of the MTJ, thus determining the programming state of the MTJ. To read another cell in the array, the transistor X1 is switched off, and the select transistor of the other cell is switched on.
The programming or write operation is accomplished by programming the MTJ at the cross-points of the bitline BL and the programming line or write wordline WWL using selective programming currents. For example, a first programming current IBL passed through the bitline BL causes a first magnetic field component in the MTJ stack. A second magnetic field component is created by a second programming current IWL that is passed through the write wordline WWL, which may run in the same direction as the read wordline RWL of the memory cell, for example. The superposition of the two magnetic fields at the MTJ produced by programming currents IBL and IWL causes the MTJ stack to be programmed. To program a particular memory cell in an array, typically a programming current is run through the write wordline WWL, which creates a magnetic field at all cells along that particular write wordline WWL. Then, a current is run through one of the bitlines, and the superimposed magnetic fields switch only the MTJ stack at the cross-point of the write wordline WWL and the selected bitline BL.
Current sensing may be used to detect a resistance change of resistive memory cells. Current sensing is the desired method of sensing the state of MRAM cells, for example. In current sensing, a voltage is applied to the bitline, and the bitline voltage is kept constant with a sense amplifier. The cell current is directly measured, with the cell current being dependent on the resistance of the memory cell being read. The use of current sensing reduces the capacitive load problem from long bitlines that may occur in voltage sensing because the voltage of the sensed lines is held constant, thereby avoiding altering charge in the different interconnection capacitances of different memory cells.
However, a limitation of a magnetic tunnel junction cell resistance sensing process as described above is the time required to charge parasitic circuit capacitance when sensing its programmed state. When a selected cell is sensed, its resistance is essentially compared to the resistance of a reference cell that might be configured with the average resistance of a cell programmed to store a “0” and a cell programmed to store a “1.” One end of the selected cell and one end of the reference cell are coupled to circuit ground and the other ends to fixed but separate voltage sources. These fixed voltage sources, such as 250 mV sources, are included to remove the voltage-dependent component of cell resistance from the measurement. The fixed voltage sources are generally configured as source followers with substantially identical output (source) voltages. To provide the same output voltages they are formed with substantially identical (or substantially proportional) semiconductor features and they conduct the same (or proportional) currents so that they exhibit the same gate-to-source voltage drops. Gate-to-source voltage drop is a highly variable characteristic of the manufacture of metal-oxide semiconductor field-effect transistors (MOSFETs), but identical devices on the same die (or even on the same wafer) can be configured to predictably have the same gate-to-source voltage drops. In addition, a current mirror is used to supply current to the cell to be sensed that is substantially identical (or substantially proportional) to the current flowing in a reference cell so that the small changes in cell resistance of the sensed cell can be reliably detected. A characteristic of the cell resistance sensing process is a preset and thus a limited current for the sensed resistance, which substantially restricts the remaining current available to charge circuit parasitic capacitance. Since circuit voltage settling time is inversely proportional to the available capacitance charging current, these prior art circuits limit the speed at which cell resistance can be sensed.
Thus, to increase the speed of sensing MRAM cell resistance and thereby its programmed state a technique is required to increase the current available to charge circuit parasitic capacitance, at least during the initial phase of the MRAM cell resistance sensing process, while providing a clamped, fixed voltage to the sensed cell during the resistance sensing process.
The devices described herein with a resistance dependent on a programmed state of a free magnetic layer are preferably based on the tunneling magnetoresistance effect (TMR), but, alternatively, may be based on other magnetic-orientation dependent resistance effects such as the giant magnetoresistance effect (GMR) or other magnetic-orientation dependent resistance effects relying on the electron charge and its magnetic moment. The programmable resistance devices described herein will generally be described as TMR devices with a resistance dependent on its programmed magnetic state, but other devices based on the GMR or other effects wherein a resistance is dependent on its magnetically programmed state may be readily substituted for the TMR devices within the broad scope of the present invention.